The present invention relates to a fuse option circuit of an integrated circuit and a method thereof. More particularly, it concerns a fuse option circuit for detecting precisely if a fuse is cut or not through comparing resistance values of a cut fuse and a fuse kept without a cutting process which are formed on a chip of an integrated circuit, in order to generate more reliable fuse option signaling.
IC products of a semiconductor use an option operating method in order to change an operational mode of a device, product or system. This conventional method is divided into a bonding option, a metal option or a fuse option Particularly, a fuse option is widely used as a repairing method for replacing an abnormal memory cell, generated during manufacturing process of a semiconductor device, with a normal memory cell. A fuse option is divided to a laser cutting method and electrical cutting method. A laser-cutting method is to radiate a laser beam to cut a fuse, as shown in FIG. 1A. An electrical cutting method is to charge an excessive electric current in order to cut a fuse, as shown in FIG. 1B.
An electrical cutting method doesn""t have to use a special cutting device for conventing a mode and repairing a memory cell, and its algorithm is very simple. Also, this method can convert a mode and repair a memory cell at the same time of test, and has an advantage that it can be also used at a package level. But the electrical cutting method is not as precise as the laser cutting method. Accordingly, there is much probability of failure in the case of the electrical cutting method and there is a disadvantage that a fuse may be linked again after cutting. Thus, the electrical cut fuse option circuit has been unreliable as compared with the laser fuse option circuit.
FIG. 2 illustrates the conventional fuse option circuit using an electrical cutting method. The fuse option circuit includes a cutting circuit 10, a fuse 12 and an output circuit of a fuse option signal 14. When an enable signal(VCCH) is applied thereto, the fuse option circuit charges or flows the file 12 with a cutting current for a predetermined time so as to cat electrically the fuse 12. Accordingly, an electric potential of a node N is changed from high level to low level by the fuse cutting in the output circuit of the fuse option signal 14, and then this low state is latched to output a fuse option signal OUT of a high state.
In the conventional fuse option circuit, a non-zero fuse resistance produces an output error in case that a fuse is not cut normally, i.e. one that is cut imprecisely as shown in FIG. 1b. And even if an error is not made, an electric current flows through a fuse that is incompletely cut as shown in FIG. 1b. Accordingly, there is the added disadvantage in prior art fuse option circuits of consuming an excessive electric power.
One aspect of the present invention is to provide a reliable fuse option circuit of an integrated circuit and a method thereof through generating a precise fuse option signal by comparing resistance values of a fuse after cutting and a reference fuse in order to overcome disadvantages of the conventional technology.
Another aspect of the present invention is to provide a fuse option circuit and method thereof for reducing power consumption generated by a fuse that is incompletely cut.
According to the present invention, a circuit comprises: a first fuse, which is formed on a chip and cut when a larger electric current is charged thereto than a set value; a second fuse formed on the chip identically with the first fuse; a fuse cutting means which provides the first fuse with a current loop in response to a fuse cutting signal; and a fuse option signal generating means which produces a fuse option signal, comparing resistance values of the first fuse and the second fuse. It is preferred that the option signal generating means is one chosen from among a CMOS inverter, a latch circuit composed of a CMOS inverter, a differential amplifier, a latch amplifier or a sense amplifier.
A fuse option method according to the present invention comprises the following steps of: arranging a first and second fuses on a chip; cutting the first fuse through charging a cutting current thereto; comparing resistance values of the first and the second fuses; and generating a fuse option signal in response to a result of comparing the resistance values.